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;EHmEHDL1AUAE9uH\$H|$PHcD$HT$@HTPH=!HcH1E1HDPHJ<IND9H|$0NH$dH3%(Hĸ[]A\A]A^A_D$D$D$D$1H\$PHt$0H=c1H=m1`f.H%D1PDHcD$HElH<1P
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veHcHf@׃	DfSHt7|-	w%H=9^1HH5 [O[fDH=^1RH%H=~wLH-HwH=a1"uJ@tH=h1HH5 [Ԛ@H=uH=Oa1ڷH=Sa1·H=a1買뎍NwSHHuu.uJ[H=a1rHH5 [BfH=]1RHH5X ["fH=\12H%H=tbw@H-HwH=`1tH=`1HH5V [H=uH=?`1ʶH=`1貶몃1v@HHtHHuHH!HЃHUlSHHcHH=[12HH5 [fDH=g1HH5 [ҘfH=_1H5k H賘HH?H[@H=Y[1誵H%H=tZwhH-HwH=^1~tH=^1hHH5 [8HH5v [ H=^12H=uH=^1HH5 [1v@HHtHxH@H!HЃf.H%t@tAG<wH
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DfvfDSH=YH1.HH5 [f.@AVAUATUSSH@dH%(HD$81=KHA1Ld$Lt$(f+88H=p1貱A9~rH
pAغ L1l>1L<tL2=HtlH=pL1K9A9@HD$8dH3%(H@[]A\A]A^H=apL1Hf.LHL$;Ht H=ipL1述of.Ll<HtH=WpL1腰5D$*H=fp17f.H5pH=6PHyHHW!tHx0H5spH=PNHH$!tHx$HH5!H=p1ܯ;H5!H=p1软;AWAVAUATUSHL%!H$0H$HL$HD$dH%(H$1MAMDžMH|$8HSAH\$@C8HL$8H|$0HZpM1#8HL$8HEKH18H|$84H{HLK1	7D$D$ D$$D$,D$(D$HL$0H<H1K17HcD$HRDH<1p7HcD$(H$HnH<1P7HcD$,HL$HnH<1/7HcD$$HnLH<17HcD$ HnLH<16HcD$HL$HpnH<16HcLH1E1HD@T@J<I3D9H|$03H$dH3%(H[]A\A]A^A_HZ1H\$@I6HL$8H|$0H`nM1)6HL$8HKIH16H|$83D$D$ D$$D$,D$(D$U4DAWAVAUATUSHL% dH%(H$1T$L$MAEƅEH|$8HPAT5DD$HL$8H|$0HmAپDl$D4$1&5H\$@HL$8HCH1H5H|$81H{HJH14D$ D$$D$,D$(D$HL$0H<H7H14HcD$HODH<1v4HcD$(L$HlH<1V4HcD$,L$HkH<164HcD$$HkDH<14HcD$ HkDH<13HcLH1E1HD@|@J<I0D9H|$00H$dH3%(H[]A\A]A^A_H1H\$@q3DL$DD$H|$0HL$8HkDl$D4$1A3HL$8HcFH1&3H|$80D$ D$$D$,D$(D$9u1DH5`kH=IHHH tHexHH5 H=k1臩}5f.AWAVAUATUSHL- dH%(H$1MAIԅH|$(HqMAH\$0A2HL$(H|$ Hj11HL$(HEH11H|$(.H{H"E1	1D$D$D$D$D$HL$ H<HE1m1J<HLD1S1HcD$I$HjH<131HcD$IL$HiH<11HcD$IL$HiH<10HcD$IL$HiH<10HcD$IL$PHiE1H<10HcH1LHD03J<I-D9H|$ t-H$dH3%(H[]A\A]A^A_H:1H\$0)0HL$(H|$ Hh1A0HL$(H(CH1/H|$(,D$D$D$D$D$&:.f.AWAAVIAUIATL%0 UH-0 SL)1HH,HtLLDAHH9uH[]A\A]A^A_Ðf.f.@H Ht
H111HHValid CPUs:not finished?
CPU %u
BANK %d
TSC %#llx
RIP %#02x:%#llx
MISC %#llx
ADDR %#llx
MCGSTATUS %#llx
PROCESSOR %u:%#x
TIME %llu
SOCKETID %u
APICID %u
MCGCAP %#llx
THERMAL EVENTUnknown vendorUndecoded extended event %xBANK %dCPU %d %s TSC %llx %sRIP%s %02x:%llx
MISC %llx ADDR %llx TIME %llu %sSTATUS %llx MCGSTATUS %llx
MCGCAP %llx APICID %x SOCKETID %x PPIN %llx
MICROCODE %x
/proc/cpuinfovendor_id : %63[^
]cpu family : %dmodel : %dcpu MHz : %lfflagsAuthenticAMDGenuineIntelRIP: %s
(Fields were incomplete)
no data in mce record
mcelog readMCE %d
consider an update
mcelog.c(pfd->revents & 0x001) != 0mcelog: mce: [Hardware Error]:CPU CPU %u BANK %u%nCPU %u %u%nMCGSTATUSMCGSTATUS %llx%nRIPRIP !INEXACT!%02x:<%016Lx> {%99s}%nTSCTSC %llx%nADDRADDR %llx%nMISCMISC %llx%nPROCESSORPROCESSOR %u:%x%nTIMETIME %llu%n%10s %10s %u %u:%u:%u %u%nMCGCAPMCGCAP %llx%nAPICIDAPICID %x%nSOCKETIDSOCKETID %u%nCPUIDHARDWARE ERROR(XEN)CPU %d(XEN) Bank %d: %llx at %llx%i,%iUnknown Intel CPU
Cannot open config file %s
dump all bios
pages
mcelog %s
CPU is unsupported
Cannot open logfile %srun-credentialsglobalfilter-memory-errorsCannot open `%s'MCE_GET_RECORD_LENMCE_GET_LOG_LENCannot change group to %dCannot change user to %ddaemonCannot open pidfile `%s'logfilek8p4genericcore2intel-cpuignorenodevno-filterno-dmidmi-verbosecpumhzsyslog-errordump-raw-asciirawno-syslogversionconfig-fileforegroundnum-errorspidfiledebug-numerrorsno-imc-loghelpis-cpu-supportedMCA:*MCi_MISC register valid*MC? status*Unsupported new Family*CyrixUMCvendor 4Centaurvendor 6TransmetaNSCp6olddunningtonxeon74xxxeon7400xeon5500xeon5200xeon5000xeon5100xeon3100xeon3200core_i7core_i5core_i3nehalemwestmerexeon71xxxeon7100tulsaintelxeon75xxxeon7500xeon7200sandybridgesandybridge-epivybridgeivybridge-epivybridge-exhaswellhaswell-ephaswell-exbroadwellbroadwell-dbroadwell-epbroadwell-exknightslandingknightsmillxeon-v4atomskylakeskylake_serverkabylakedenvertongeneric CPUIntel PPro/P2/P3/old XeonIntel CoreAMD K8 and derivatesIntel P4Intel Xeon 7400 seriesIntel Xeon 7100 seriesIntel Xeon 7500 seriesSandy BridgeSandy Bridge EPIvy BridgeIvy Bridge EP/EXHaswellHaswell EP/EXBroadwellKnights LandingKnights MillATOMSkylakeSkylake serverKabylakeDenverton/dev/mcelogTimeout waiting for exception on other CPUsCPUID Vendor %s Family %u Model %u
ERROR: AMD Processor family %d: mcelog does not support this processor.  Please use the edac_mce_amd module instead.
warning: Cannot parse /proc/cpuinfo
warning: Cannot open /proc/cpuinfo
Unknown CPU type vendor %u family %u model %uForced cputype %s does not match cpu type %s from mcelog
Hardware event. This is not a software error.
Warning: MCE buffer is overflowed.
warning: %lu bytes ignored in each record
WARNING: with --dmi mcelog --ascii must run on the same machine with the
     same BIOS/memory configuration as where the machine check occurred.
CPU %u: Machine Check Exception: %16Lx Bank %d: %016Lx%nCPUID Vendor %30s Family %u Model %u
The hardware reports a non fatal, correctable incident occurredUsage:

  mcelog [options]  [mcelogdevice]
Decode machine check error records from current kernel.

  mcelog [options] --daemon
Run mcelog in daemon mode, waiting for errors from the kernel.

  mcelog [options] --client
Query a currently running mcelog daemon for errors

  mcelog [options] --ascii < log
  mcelog [options] --ascii --file log
Decode machine check ASCII output from kernel logs

Options:
--version           Show the version of mcelog and exit
--cpu CPU           Set CPU type CPU to decode (see below for valid types)
--intel-cpu FAMILY,MODEL  Set CPU type for an Intel CPU based on family and model from cpuid
--k8                Set the CPU to be an AMD K8
--p4                Set the CPU to be an Intel Pentium4
--core2             Set the CPU to be an Intel Core2
--generic           Set the CPU to a generic version
--cpumhz MHZ        Set CPU Mhz to decode time (output unreliable, not needed on new kernels)
--raw		     (with --ascii) Dump in raw ASCII format for machine processing
--daemon            Run in background waiting for events (needs newer kernel)
--client            Query a currently running mcelog daemon for errors
--ignorenodev       Exit silently when the device cannot be opened
--file filename     With --ascii read machine check log from filename instead of stdin
--logfile filename  Log decoded machine checks in file filename
--syslog            Log decoded machine checks in syslog (default stdout or syslog for daemon)
--syslog-error	     Log decoded machine checks in syslog with error level
--no-syslog         Never log anything to syslog
--logfile filename  Append log output to logfile instead of stdout
--dmi               Use SMBIOS information to decode DIMMs (needs root)
--no-dmi            Don't use SMBIOS information
--dmi-verbose       Dump SMBIOS information (for debugging)
--filter            Inhibit known bogus events (default on)
--no-filter         Don't inhibit known broken events
--config-file filename Read config information from config file instead of /etc/mcelog/mcelog.conf
--foreground        Keep in foreground (for debugging)
--num-errors N      Only process N errors (for testing)
--pidfile file	     Write pid of daemon into file
--no-imc-log	     Disable extended iMC logging
--is-cpu-supported  Exit with return code indicating whether the CPU is supported
--help	             Display this message.
Unknown CPU type `%s' specified
Cannot open input file `%s': %s
Kernel does not support page offline interfaceIntel Xeon 5500 series / Core i3/5/7 ("Nehalem/Westmere")Intel generic architectural MCAIntel Xeon (Broadwell) D familyIntel Xeon v4 (Broadwell) EP/EX/etc/mcelog/mcelog.confprocess_mcefdUNKNOWNMCG status:RIPV EIPV MCIP LMCE MCi status:
Machine check not valid
Error overflow
Uncorrected error
Corrected error by %s
Corrected error
Error enabled
MCi_MISC register valid
MCi_ADDR register valid
Processor context corrupt
MCA: %s TLB %s Error
%s CACHE %s %s Error
Memory as cache: Internal Timer error
Unknown Error %x
Model:FSB address parityResponse hard failResponse parityPIC and FSB data parityPad state machinePad strobe glitchPad address glitchRequest-did-not-timeoutRequest-timed-outMemory-accessReservedIOOther-transactionGenericData-ReadData-WriteInstruction-FetchPrefetchEvictionSnoopLocal-CPU-originated-requestResponed-to-requestObserved-error-as-third-partyLevel-0Level-1Level-2Level-3InstructionDataUnknownNo ErrorUnclassifiedMicrocode ROM parity errorExternal errorFRC errorInternal parity errorgreenres3eccUCNASRAOSRARProcessor %d heated above trip temperature. Throttling enabled.
Please check your system cooling. Performance will be impacted
Processor %d below trip temperature. Throttling disabled
Firmware may have updated this error
Threshold based error status: %s
corrected filtering (some unreported errors in same region)
%s Generic cache hierarchy error
Internal unclassified error: %x
BUS error: %d %d %s %s %s %s %s
IO MCA reported by root port %x:%02x:%02x.%x
Invalid PIC request(Signature=0xF04H)SMM Handler Code Access Violationyellow
Large number of corrected cache errors. System operating, but might lead
to uncorrected errors soonmirroring with channel failovermirroring. Primary channel scrubbed successfullyFFF4JFtFtF4JLF4J$F4JEE4J4J4J4JE4JEBI(GBHI(G(GHIB(G       bit%d = %s
  Northbridge %s
  ECC syndrome = %x
  Chipkill ECC syndrome = %x
  link number = %x
Bus or cacheCache tag  L2 cache ECC error
  %s array error
physicalvirtual found by scrubber%u %sUnknown threshold counterMC4_MISC0 DRAM thresholdMC4_MISC1 Link thresholdMC4_MISC2 L3 Cache thresholdMC4_MISC3 FBDIMM thresholderr cpu0err cpu1err cpu2err cpu3error found by scrubsublink or DRAM channelL3 subcache in error bit 0L3 subcache in error bit 1res12uncorrected ecc errorres23res24processor context corrupterror address validmisc error validerror enableerror uncorrectedRAM ECC errorCRC errorSync errorMaster abortTarget abortGART errorRMW errorWatchdog errorRAM Chipkill ECC errorDEV ErrorLink Data ErrorLink Protocol ErrorNB Array ErrorDRAM Parity ErrorLink RetryTablew Walk Data ErrorL3 Cache Data ErrorL3 Cache Tag ErrorL3 Cache LRU Errorres.i/orequest didn't time outrequest timed outlocal node originlocal node responselocal node observedgeneric participationgeneric errorgeneric readgeneric writedata readdata writeinstruction fetchprefetchevictsnoop?instructiondatareserveddata cacheinstruction cachebus unitload/store unitnorthbridgefixed-issue reoder  TLB error '%s transaction, level %s'
  memory/cache error '%s mem transaction, %s transaction, level %s'
  bus error '%s, %s
             %s mem transaction
             %s access, level %s'
  Instruction cache ECC error
  TLB parity error in %s array
  Data cache ECC error (syndrome %x)  Threshold error count overflow
  no decoder for unknown bank %u
error overflow (multiple errors)<GGGGG]GG]GlGlength %d handle %x
string %s
hnd %x size %d expected %d
entry %x disabled
RANGESDMI_DIMMS/sys/firmware/efi/systab/proc/efi/systab/dev/memSMBIOS_SM_Cannot find SMBIOS DMI tables<%u>%hu Mhz NoneDevice Locator: %s
Bank Locator: %s
Manufacturer: %s
Serial Number: %s
Asset Tag: %s
Part Number: %s
OtherFast-pagedStatic ColumnPseudo staticRAMBUSSynchronousCMOSEDOWindow DRAMCache DRAMNon-volatileRegisteredUnbufferedLRDIMMEDRAMVRAMSRAMFLASHEEPROMFEPROMCDRAM3DRAMSDRAMSGRAMRDRAMDDR2 FB-DIMMReserved 0x15Reserved 0x16Reserved 0x17FBD2LPDDRLPDDR2LPDDR3LPDDR4SIMMSIPChipDIPZIPProprietary CardTSOPRow of chipsSODIMMSRIMMhandle %x length %d truncated
/sys/firmware/dmi/entries/%hhu-%d/rawCan't build pathname for DMI type %hhu instance %d
range %x-%x h %x a %x row %u ilpos %u ildepth %u
dimm h %x width %u datawidth %u size %u set %u
/sys/firmware/dmi/entries/0-0/rawCannot open /dev/mem for DMI decoding: %sNo valid SMBIOS entry point: Continue without DMI decoding%s: SMBIOS entry point at 0x%08lx
Cannot mmap 0x%lx for efi mode: %sCannot mmap 0xf0000 for legacy mode: %sDMI tables at %x, %u bytes, %u entries
Cannot mmap SMBIOS tables at %xNot enough unique address ranges. SMBIOS DIMM sanity check failedMissing locator. SMBIOS DIMM sanity check failedAmbiguous locators `%s'<->`%s'. SMBIOS DIMM sanity check failed
WARNING: SMBIOS data is often unreliable. Take with a grain of salt!
Memory device for address %llx too short %u
Width %hu Data Width %hu Size %u %s
No DIMM found for %llx in SMBIOS
[at %.0f Mhz %u days %u:%u:%u uptime (unreliable)]/sys/devices/system/cpu/cpu%d/cpuidle/proc/acpi/processor/CPU%d/power/sys/devices/system/cpu/cpu%d/cpufreq/cpuinfo_max_freqnonstop_tscconstant_tsc C%d:usageusage[%d]/sys/devices.AC@@PIC or FSB data parity errorBINIT observedMCE is observedMCE drivenBERR on this CPUuncorrectable ECC errorfailure that caused IERRinternal BINITBQ_ERR_HARD_TYPEBQ_ERR_DOUBLE_TYPEBQ_ERR_AERR2_TYPEBQ_ERR_SINGLE_TYPEBQ_ERR_AERR1_TYPEBQ_DCU_READ_TYPEBQ_IFU_DEMAND_TYPEBQ_IFU_DEMAND_NC_TYPEBQ_DCU_RFO_TYPEBQ_DCU_RFO_LOCK_TYPEBQ_DCU_ITOM_TYPEBQ_DCU_WB_TYPEBC_DCU_WCEVICT_TYPEBQ_DCU_WCLINE_TYPEBQ_DCU_BTM_TYPEBQ_DCU_INTACK_TYPEBQ_DCU_INVALL2_TYPEBQ_DCU_FLUSHL2_TYPEBQ_DCU_PART_RD_TYPEBQ_DCU_PART_WR_TYPEBQ_DCU_SPEC_CYC_TYPEBQ_DCU_IO_RD_TYPEBQ_DCU_IO_WR_TYPEBQ_DCU_LOCK_RD_TYPEBQ_DCU_LOCK_WR_TYPEBQ_DCU_SPLOCK_RD_TYPEFSB address parity error detectedReceived hard error response on split transaction (Bus BINIT)BINIT received from external bustwo failing bus transactions with address parity error (AERR)bus transaction received hard error responsetimeout BINIT (ROB timeout). No micro-instruction retired for some timereceived parity error on response transaction<%u:%llx>%s%s%llu%%s: %s
Family 6 Model %u CPU: only decoding architectural errors
Family %u Model %u CPU: only decoding architectural errors
Unknown Intel CPU type family %u model %u
$_D_D_D_D_D__D_^D_^D_D_^D_D_D_D_$^Transaction: %s
Generic undefined requestMemory read errorMemory write errorAddress/Command errorMemory scrubbing errorReserved 5Reserved 6Reserved 7GENRDWRACRES5RES6RES7Received an invalid CMPDInvalid S-state transitionMemory DIMM ID of errorMemory channel ID of errorMemory ECC syndromeMemory MISC reserved 25..37Memory MISC reserved 53..56Memory address parity errorMemory internal RTID invalidMemory access out of rangeMemory reserved 20Memory write parity errorMemory read ECC errorQPI Request Transaction IDQPI miscreserved 19-23QPI misc reserved 15QPI misc reserved 14QPI reserved 21QPI reserved 20QPI header had bad parityMEMORY CONTROLLER %s_CHANNEL%s_ERR
Internal machine check status reserved 16..23Internal machine check status reserved 32..56Reset firmware did not completeInvalid Power Management RequestVID controller does not match POC controller selectedMSID from POC does not match CPU MSIDMemory transaction Tracker ID (RTId)Memory corrected error count (CORE_ERR_CNT)Memory byte enable parity errorMemory error in half of redundant memoryMemory ECC error occurred during scrubQPI class and opcode of packet with errorQPI Requestor/Home Node ID (RHNID)QPI Interleave/Head Indication Bit (IIB)Clock jitter detected in internal QPI clockingQPI Sender sent a failed response to receiverSender sent too many QPI flits to the receiverQPI credit type is not supportedQPI received unsupported message encodingReceived QPI data packet that was poisoned by senderNumber of QPI retries exceededQPI Data packet had bad parityUncorrectable ECC event on outgoing core 2 dataUncorrectable ECC event on outgoing core 1 dataUncorrectable ECC event on outgoing core 0 dataCorrectable ECC event on outgoing core 2 dataCorrectable ECC event on outgoing core 1 dataCorrectable ECC event on outgoing core 0 dataIntel Cache Safe Technology Queue full error
or disabled ways in a set overflowQuiet cycle timeout error (correctable)Write Exclusive error from core 0Write Exclusive error from core 1Write exclusive error from core 2Parity data error on inbound data detectedParity error on FSB response field detectedHard Failure response received for a local transactionParity error detected during FSB request phaseInternal timeout errorInclusion error from core 0Inclusion error from core 1Inclusion error from FSBSNP stall error from FSBWrite stall error from FSBFSB Arbiter Timeout errorInclusion error from core 2MISC format %llx value %llx
Corrected eventsUncorrectable ECC event on outgoing FSB dataCorrectable ECC event on outgoing FSB dataEnhanced Intel SpeedStep Technology TM1-TM2 ErrorCBC OOD Queue Underflow/overflowPad logic detected a request strobe glitch or sequencing errorPad logic detected a data strobe glitch or sequencing errorData ECC event to error on inbound data correctable or uncorrectableDetected an Enhanced Defer parity error phase A or phase BData parity error on data received from Core 1 detectedData parity error on data received from Core 0 detectedFSB data parity error on inbound date detectedPartity error detected on Core 1 request's address fieldPartity error detected on Core 0 request's address fieldconfig file line %d: %s
[%s] %sHeader without ending ]numericalchoice--conf%s-threshold%s-triggerTrigger `%s' not executable
%s-log%s-user%s-groupyestruenofalseoff%s config option `%s' unparseable
left over characters at end of lineconfig file line not field nor headerUnknown user `%s' in %s:%s config entry
Unknown group `%s' in %s:%s config entry
out of memoryCannot reopen logfile `%s'Cannot set FD_CLOEXEC flag on fdpoll table overfloweventloop.ci >= 0 && i < max_pollfdpoll errorunregister_pollcbnot enabled%u in %u%c%u %1s / %u %1s%u / %u %1s%s:
	%lu total
	%s
/sbin:/usr/sbin:/bin:/usr/bin%ld%s: %sLocation %s
PATHPATH=%sTHRESHOLD=%sTOTALCOUNT=%luDMI_LOCATION=%sDMI_NAME=%sDIMM=%dCHANNEL=%dSOCKETID=%dCECOUNT=%luUCCOUNT=%luLASTEVENT=%luAGETIME=%uMESSAGE=%sTHRESHOLD_COUNT=%dUnMemory errors
SOCKET %u CHANNEL any CHANNEL %d DIMM any DIMM %dDMI_NAME "%s"DMI_LOCATION "%s"uncorrected memory errorsdimm-tracking-enableddimmsocket-tracking-enabledmem-ce-errormem-uc-errordmi-prepopulate_Node%u_Channel%u_Dimm%uNODE %u CHANNEL %u DIMM %uNode%u_Bank%uA%u_BANK%uSocketSOCKET:%d CHANNEL:%s DIMM:%s [%s%s%s]%scorrected %s memory error count exceeded thresholdCannot account memory errors because kernel does not report socketidFallback %s memory error count %d exceeded thresholdfailed to prefill DIMM database from DMI dataping
pong
server.ccc->inbuf == ((void *)0)permission denied
cc->outbuf == ((void *)0)dumpbiosUnknown dump parameter
pagesdone
pingUnknown command
mcelog server too busy
socket-pathinitial-ping-timeoutcannot open listening socket/var/run/mcelog-clientDid not receive credentials over client unix socket %p
rejected client access from pid:%u uid:%u gid:%u
error while reading from clientaccept failed on client socketCannot enable credentials passing on client socketClient socket path `%s' too long for unix socketmcelog server already running
Cannot bind to client unix socket `%s'process_cmdclient_inputTrigger `%s' exited with status %d
Trigger `%s' died with signal %s
Too many trigger children running already
Cannot create process for triggerCannot access trigger directory `%s'Cannot collect child %dRunning trigger `%s'
children-maxdirectoryclient socketclient connectclient command writeclient read/sys/devices/system/cpucpu%u%s/%s/cache%s/index%dlevelshared_cpu_mapcache.clen == c * sizeof(unsigned)No caches found in sysfsUnifiedCannot read cache topology from %sCannot find sysfs cache for CPU %dparse_cpumapCannot read sysfs field %s/%sCannot parse number in sysfs field %s/%s
sysfs field %s/%s has unknown string value `%s'
CPU %d on socket %dCPU=%dLEVEL=%dTYPE=%sAFFECTED_CPUS=%s%uAFFECTED_CPUS=unknowncache-threshold-triggercache-threshold-log%s has large number of corrected cache errors in %s %sSystem operating correctly, but might lead to uncorrected cache errors soon
Cannot access cache threshold trigger `%s'Corrected memory errors on page %llx exceed threshold %s/sys/devices/system/memory/soft_offline_pageSoft offlining of page %llx failed, trying hard offlining
/sys/devices/system/memory/hard_offline_pageOfflining page %llx failed: %s
Per page corrected memory statistics:
%llx: total %lu seen "%s" %s%s
Kernel does not support page offline interface
Offlining page %llx
%#llx triggeredmemory-cepagememory-ce-actionaccountsoftsoft-then-hardonlineofflineoffline-failedPCU: QPI
MemCtrl: Uncorrected spare errorCorrected spare errorCorrected patrol scrub errorAddress parity errorMC_IMC_FORCE_SR_S3_TIMEOUTMC_MC_CPD_UNCPD_ST_TIMEOUTMC_PKGS_SAFE_WP_TIMEOUTMC_MORE_THAN_ONE_LT_AGENTMC_INVALID_PKGS_REQ_PCHMC_INVALID_PKGS_REQ_QPIMC_INVALID_PKGS_RES_QPIMC_INVALID_PKGC_RES_PCHMC_INVALID_PKG_STATE_CONFIGMC_WATCHDG_TIMEOUT_PKGC_SLAVEMC_HA_FAILSTS_CHANGE_DETECTEDNo errorNon_IMem_SelI_Parity_ErrorBad_OpCodeI_Stack_UnderflowI_Stack_OverflowD_Stack_UnderflowD_Stack_OverflowNon-DMem_SelD_Parity_Error`UPP    Uncorrected patrol scrub errorHA Wrt byte enable parity errorHA Wrt buffer Data parity errorMC_PECI_MAILBOX_QUIESCE_TIMEOUTMC_WATCHDG_TIMEOUT_PKGC_MASTERMC_WATCHDG_TIMEOUT_PKGS_MASTERMC_RECOVERABLE_DIE_THERMAL_TOO_HOTiMC, WDB, parity errorsCorrected memory read errorMC_CRITICAL_VR_FAILEDMC_ICC_MAX-NOTSUPPORTEDMC_PCIE_R2PCIE-RW_BLOCK_ACK_TIMEOUTIntel TXT errors Other UBOX Internal errors PCU internal error QPI: DDR3 address parity errorRBT used un-initialized valueLink failover clock failoverMC_MESSAGE_CHANNEL_TIMEOUTMC_CPD_UNCPD_SD_TIMEOUTMC_DMI_TRAINING_TIMEOUTMC_DMI_CPU_RESET_ACK_TIMEOUTMC_SVID_COMMAN_TIMEOUTMC_VR_VOUT_MAC_LT_FUSED_SVIDMC_PKGC_WATCHDOG_HANG_CBZ_UPMC_ICC_MAX_NOTSUPPORTEDMC_VID_RAMP_DOWN_FAILEDMC_EXCL_MODE_NO_PMREQ_CMPMC_BOOT_VID_TIMEOUT_DRAM_0MC_BOOT_VID_TIMEOUT_DRAM_1MC_BOOT_VID_TIMEOUT_DRAM_2MC_BOOT_VID_TIMEOUT_DRAM_3MC_SVID_COMMAND_ERRORMC_FIVR_CATAS_OVERVOL_FAULTMC_FIVR_CATAS_OVERCUR_FAULTMC_SVID_PKGC_REQUEST_FAILEDMC_SVID_IMON_REQUEST_FAILEDMC_SVID_ALERT_REQUEST_FAILEDMC_INVALID_PKGS_RSP_QPIMC_INVALID_PKGS_RSP_PCHMC_IMC_RW_SMBUS_TIMEOUTMC_MSGCH_PMREQ_CMP_TIMEOUTMC_BIOS_RST_CPL_INVALID_SEQMC_MORE_THAN_ONE_TXT_AGENTDDR4 command address parity erroriMC write data buffer parity errorUncorrected HA data byte enable errorUncorrected HA write data errorIntel QPI physical layer detected drift buffer alarmIntel QPI physical layer detected latency buffer rolloverIntel QPI link layer detected control error from R3QPIRx entered LLR abort state on CRC errorUnsupported or undefined packetIntel QPI link layer control errorIntel QPI physical layer detected a QPI in-band reset but aborted initializationLink failover data self healingPhy detected in-band reset (no width change)Rx detected CRC error - successful LLR after Phy re-initRx detected CRC error - successful LLR without Phy re-initMC_VR_ICC_MAX_LT_FUSED_ICC_MAXMC_PKGC_WATCHDOG_HANG_CBZ_DOWNMC_PKGC_WATCHDOG_HANG_C3_UP_SFMC_SVID_READ_REG_ICC_MAX_FAILEDMC_SVID_WRITE_REG_VOUT_MAX_FAILEDMC_HA_IMC_RW_BLOCK_ACK_TIMEOUTMC_WATCHDOG_TIMEOUT_PKGC_SLAVEMC_WATCHDOG_TIMEOUT_PKGC_MASTERMC_WATCHDOG_TIMEOUT_PKGS_MASTERUbox error MCA_PKGC_DIRECT_WAKE_RING_TIMEOUTM2M: MscodBucket1ErrMscodParErrMscodTimeoutMscodBgfErrMscodFullWrErrMscodPtlWrErrMscodDataRdErrUnrecognized request typeUnexpected read responseCompletion FIFO overflowCorrectable parity errorUncorrectable errorERID FIFO overflowError on Write creditsError on Read creditsScheduler errorError eventWDB read parity errorAny HA read errorHA write data parity errorLink Layer Tx Parity ErrorRouteback Table errorRF parity errorUnexpected Retry.Req flitUnexpected Retry.Ack flitPhy Control ErrorUC Phy Initialization FailureUC LL or Phy control errorCOR Phy initialization abortCOR Phy resetMCA_DMI_TRAINING_TIMEOUTMCA_DMI_CPU_RESET_ACK_TIMEOUTMCA_MORE_THAN_ONE_LT_AGENTMCA_BIOS_RST_CPL_INVALID_SEQMCA_MESSAGE_CHANNEL_TIMEOUTMCA_MSGCH_PMREQ_CMP_TIMEOUTMCA_PKGC_INVALID_RSP_PCHMCA_PKGC_WATCHDOG_HANG_CBZ_UPMCA_SVID_COMMAND_TIMEOUTMCA_SVID_CRITICAL_VR_FAILEDMCA_SVID_SA_ITD_ERRORMCA_SVID_READ_REG_FAILEDMCA_SVID_WRITE_REG_FAILEDMCA_SVID_PKGC_INIT_FAILEDMCA_SVID_PKGC_CONFIG_FAILEDMCA_SVID_PKGC_REQUEST_FAILEDMCA_SVID_IMON_REQUEST_FAILEDMCA_SVID_ALERT_REQUEST_FAILEDMCA_FIVR_CATAS_OVERVOL_FAULTMCA_FIVR_CATAS_OVERCUR_FAULTMCA_PKGS_CPD_UNCPD_TIMEOUTMCA_PKGS_INVALID_REQ_PCHMCA_PKGS_INVALID_REQ_INTERNALMCA_PKGS_INVALID_RSP_INTERNAL@9999OXHHHHHHRead response to an invalid scoreboard entryDDR4 completion to an invalid scoreboard entryCompletion to an invalid scoreboard entryInterrupt received while outstanding interrupt was not ACKedUncorrected address parity errorHA write byte enable parity errorLink Layer reset initiated while protocol traffic not idleLink Layer Reset still in progress when Phy enters L0Rx Header-or-Credit BGF credit overflow/underflowunexpected Tx Protocol flit (EOP, Header or Data)UC Phy detected drift buffer alarmUC Phy detected latency buffer rolloverUC LL Rx detected CRC error: unsuccessful LLR: entered abort stateUC LL Rx unsupported or undefined packetUC LL Rx parameter exchange exceptionUC LL detected control error from the link-mesh interfaceCOR Phy lane failure, recovery in x8 widthCOR Phy L0c error corrected without Phy resetCOR Phy L0c error triggering Phy ResetCOR Phy L0p exit error corrected with Phy resetCOR LL Rx detected CRC error - successful LLR without Phy ReinitCOR LL Rx detected CRC error - successful LLR with Phy ReinitMCA_BIOS_INVALID_PKG_STATE_CONFIGMCA_PKGC_WATCHDOG_HANG_CBZ_DOWNMCA_PKGC_WATCHDOG_HANG_C3_UP_SFMCA_SVID_VCCIN_VR_ICC_MAX_FAILUREMCA_SVID_VCCIN_VR_VOUT_FAILUREMCA_SVID_CPU_VR_CAPABILITY_ERRORMCA_SVID_MCP_VR_ABSENT_OR_RAMP_ERRORMCA_SVID_UNEXPECTED_MCP_VR_DETECTEDMCA_WATCHDOG_TIMEOUT_PKGC_SLAVEMCA_WATCHDOG_TIMEOUT_PKGC_MASTERMCA_WATCHDOG_TIMEOUT_PKGS_MASTERMCA_PKGS_SMBUS_VPP_PAUSE_TIMEOUTMCA_RECOVERABLE_DIE_THERMAL_TOO_HOTWDB read ECCUncorrected demand read errorCmd/Addr parityCorrected Demand/Patrol Scrub Error/dev/cpu/%d/msrWarning: cpu %d offline?, imc_log not set
Cannot open %s to set imc_log
Cannot read MSR_ERROR_CONTROL from %s
Cannot write MSR_ERROR_CONTROL to %s
Cannot re-read MSR_ERROR_CONTROL from %s
No DIMM detection available on cpu %d (normal in virtual environments)
bus-uc-threshold-triggeriomca-threshold-triggerLEVEL=%sPARTICIPATION=%sREQUEST=%sORIGIN=%sTIMEOUT=%sSEG=%xBUS=%02xDEVICE=%02xFUNCTION=%xCannot access bus threshold trigger `%s'Cannot access iomca threshold trigger `%s'%s received Bus and Interconnect Errors in %s%s received IO MCA Errors from %x:%02x:%02x.%xunknown-threshold-trigger%s received unknown errorMISC=%llxADDR=%llxMCGSTATUS=%llxMCGCAP=%llxCannot access unknown threshold trigger `%s';	0 Hx0 P`p@@@0p	0@	@X			P@h0```@
 



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